1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device such as a dynamic random-access memory.
2. Description of Related Art
In an operation test of a semiconductor integrated circuit device, the number of pins for testing must be as many as the number of total pads. However, as the number of pins increases, cost rises. Accordingly, a conventional semiconductor integrated circuit device includes a common circuit for sharing part of the pads at the time of testing as disclosed in JP 9(1997)-92787 A, for example.
Further, in a semiconductor integrated circuit device with a configuration in which, besides an external power supply supplied externally, an internal power supply generated based on the external power supply is used, external pads are necessary for monitoring the internal power supply at the time of testing memories or the like or for forcibly applying a voltage externally instead of an internal power supply. As illustrated in FIG. 9, which shows a configuration of the conventional semiconductor integrated circuit device, external pads 108 for the above-mentioned internal power supply are provided at an external pad region 102 of a semiconductor integrated circuit device 101.
However, for inputting the external power supply or for monitoring the internal power supply at the time of memory test, it is necessary to provide at least as many external pads 108 as the number of internal power supply generating circuits 105 of embedded memories 103. Thus, when there are many memories 103, the number of the monitor pads 108 also increases accordingly.
The semiconductor integrated circuit device 101 with a logic circuit and a plurality of memories embedded in a single chip, which is called a system LSI and has been used commonly in recent years, has a high-pin-count configuration when considering the number of pins for the logic circuit as well. Consequently, in order to achieve a smaller area, it has becomes absolutely necessary to reduce the number of external pads used for memory test.
Moreover, since the number of pins that can be monitored by a memory tester is limited, complex adjustment has to be made for memory test when the number of the external pads 108 exceeds the limited number of pins. This also causes a problem that a test time cannot be shortened. On the other hand, in a semiconductor integrated circuit device having degenerate functions that are as many as I/Os, like the above-described semiconductor integrated circuit device disclosed in JP 9-92787 A, since characteristics of an internal power supply voltage vary between a normal operation period and a memory test period, the internal power supply voltage cannot be evaluated accurately.